FPT2012 Photo Gallery

Click the link below to open the gallery window.

1. Photo Gallery Dec. 10. 2012 (Monday)
2. Photo Gallery Dec. 11. 2012 (Tuesday)
3. Photo Gallery Dec. 12. 2012 (Wednesday)

Final Program with Presentation Slides

Monday Dec. 10
8:00		Registration	Lobby
8:45
8:45		Opening	Mugunghwa Hall
9:00
9:00		Session 1.1 Keynote I	Mugunghwa Hall
		Chair: Soo-Ik Chae, Seoul National University
		Multiscale Dataflow for Maximum Performance Computing
10:00		Dr. Oskar Mencer, CEO of Maxceler Technologies
10:00		Coffee Break	Lobby
10:20
10:20		Session 1.2 Design Methods and Techniques for FPGAs	Mugunghwa Hall
		Chair: Vaughn Betz, University of Toronto
	1.2.1	Rapid RTL-based Signal Ranking for FPGA Prototyping
		Steven J.E Wilton1,  Bradley R. Quinton2,  Eddie Hung1
		1University of British Columbia, 2Tektronix
	1.2.2	K-Way Partitioning Based Packing for FPGA Logic Blocks without Input Bandwidth Constraint
		Wenyi Feng
		Microsemi Corporation
	1.2.3	Neural Network Based Pre-placement Wirelength Estimation
		Qiang Liu,  Jianguo Ma,  Qijun Zhang
		Tianjin University
	1.2.4	Heterogeneous Configuration Memory Scrubbing for Soft Error Mitigation in FPGAs
		Ju-Yueh Lee1,  Cheng-Ru Chang1,  Naifeng Jing2,  Naifeng Jing2, Juexiao Su1, Shijie Wen3, Rich Wong3, Lei He1
11:40		1University of California, Los Angeles, 2Shanghai Jiao Tong University, 3Cisco System Inc.
11:40		Poster Paper Presentations	Mugunghwa Hall
12:00
Monday Dec. 10
12:00		Session 1.3 Posters & Coffee Break	Lobby
		Chair: Yoonjin Kim, Sookmyung Women's University
	1.3.1	FPGA based Memory Efficient High Resolution Stereo Vision System for Video Tolling
		Yi Shan1,  Zilong Wang1,  Wenqiang Wang1,  Yuchen Hao1,  Yu Wang1,  Kuenhung Tsoi2,  Wayne Luk2,  Huazhong Yang1
		1Tsinghua University, 2Imperial College London
	1.3.2	A Task-Level OOO Framework for Heterogeneous Systems
		Junneng Zhang,  Chao Wang,  Peng Chen,  Xuehai Zhou,  Xi Li
		University of Science and Technology of China
	1.3.3	FPGA-GPU-CPU Heterogenous Architecture for Real-time Cardiac Physiological Optical Mapping
		Pingfan Meng,  Matthew Jacobsen,  Ryan Kastner
		University of California, San Diego
	1.3.4	Managing Mutex Variables in a Cache-Coherent Shared-Memory System For FPGAs
		Vincent Mirian and Paul Chow
		University of Toronto
	1.3.5	FPGA Optimized Packet-Switched NoC using Split and Merge Primitives
		Yutian Huan and Andre DeHon
		University of Pennsylvania
	1.3.6	Parallel Dataflow Execution for Sequential Programs on Reconfigurable Hybrid MPSoCs
		Chao Wang1,  Xi Li1,  Xuehai Zhou1,  Yajun Ha2
		1University of Science and Technology of China, 2National University of Singapore
	1.3.7	Guppy: A GPU-like Soft-Core Processor
		Abdullah Al-Dujaili1,  Florian Deragisch2,  Andrei Hagiescu3,  Weng-Fai Wong3
		1Nanyang Technological University, 2ETH Zurich, 3National University of Singapore
	1.3.8	A High Speed Open Source Controller for FPGA Partial Reconfiguration
		Kizheppatt Vipin and Suhaib A Fahmy
		Nanyang Technological University
	1.3.9	Design Space Exploration and Implementation of a High Performance and Low Area Coarse Grained Reconfigurable Processor
		Dongkwan Suh,  Kiseok Kwon,  Sukjin Kim,  Soojung Ryu,  Jeongwook Kim
12:40		Samsung Electronics
12:40		Lunch	Hoam Faculty House
14:00
Monday Dec. 10
14:00		Session 1.4 FPGA Architectures and Networks	Mugunghwa Hall
		Chair: Andre Dehon, University of Pennsylvania
	1.4.1	Small Virtual Channel Routers on FPGA Through Block RAM Sharing
		Jimmy Kwa and Tor Aamodt
		University of British Columbia
	1.4.2	uBRAM-based Run-time Reconfigurable FPGA and Corresponding Reconfiguration Methodology
		Yi-Chung Chen1,  Wenhua Wang1,  Wei Zhang2,  Hai (Helen) Li1
		1Polytechnic Institute of NYU, 2Nanyang Technological University
	1.4.3	An FPGA with Power-Gated Switch Blocks
		Assem A.M. Bsoul and Steven J.E. Wilton
		University of British Columbia
	1.4.4	Design Tradeoffs for Hard and Soft FPGA-based Networks-on-Chip
		Mohamed S. Abdelfattah and Vaughn Betz
15:20		University of Toronto
15:20		Poster Paper Presentations	Mugunghwa Hall
15:40
Monday Dec. 10
15:40		Session 1.5 Posters & Coffee Break	Lobby
		Chair: Jaeha Kim, Seoul National University
	1.5.1	Rule-Based Data Communication Optimization Using Quantitative Communication Profiling
		Cuong Pham-Quoc,  Zaid Al-Ars,  Koen Bertels
		Delft University of Technology
	1.5.2	Parametric Reconfigurable Designs with Machine Learning Optimizer
		Maciej Kurek and Wayne Luk
		Imperial College London
	1.5.3	Option Space Exploration Using Distributed Computing for Efficient Benchmarking of FPGA Cryptographic Modules
		Benjamin Brewster,  Ekawat Homsirikamol,  Rajesh Velegalati,  Kris Gaj
		George Mason University
	1.5.4	A Study of Adaptable Co-processors for Cyclic Redundancy Check on an FPGA
		Amila Akagic and Hideharu Amano
		Keio University
	1.5.5	Side-Channel Resistant AES Architecture Utilizing Randomized Composite Field Representations
		Bernhard Jungk1,2,  Marc Stöttinger3,  Jan Gampe1,  Steffen Reith1,  Sorin A. Huss3
		1Hochschule Rhein-Main, 2easycore GmbH, 3Technische Universität Darmstadt
	1.5.6	Resiliency-aware Scheduling: Resource Allocation for Hardened Computation on Configurable Devices
		Jeremy Abramson and Pedro C. Diniz
		University of Southern California
	1.5.7	FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm
		Server Kasap and Soydan Redif
		European University of Lefke
	1.5.8	Automatic Rectification of Design Errors in Complex Processors with Programmable Hardware
		Amir Masoud Gharehbaghi and Masahiro Fujita
		University of Tokyo
	1.5.9	Verification of Streaming Hardware and Software Codesigns
		Tim Todman,  Peter Boehm,  Wayne Luk
16:20		Imperial College London
Monday Dec. 10
16:20		Session 1.6 Soft Processors and Object Detectors	Mugunghwa Hall
		Chair: Tulika Mitra, National University of Singapore
	1.6.1	iDEA: A DSP Block Based FPGA Soft Processor
		Hui Yan Cheah,  Suhaib Fahmy,  Douglas L. Maskell
		Nanyang Technological University
	1.6.2	A Memory-Efficient Parallel Single Pass Architecture for Connected Component Labeling of Streamed Images
		Michael Klaiber,  Lars Rockstroh,  Zhe Wang,  Yousef Baroud,  Sven Simon
		University of Stuttgart
	1.6.3	An Energy-Efficient, Fast FPGA Hardware Architecture for OpenCV-Compatible Object Detection
		Braiden Brousseau and Jonathan Rose
		University of Toronto
	1.6.4	A High-Performance Architecture for Training Viola-Jones Object Detectors
		Charles Lo and Paul Chow
17:40		University of Toronto
17:40		Reception	Lobby
20:00
18:00		Preliminary Design Competition	Mugunghwa Hall
		Chair: Chanho Lee, Soongsil University
20:00		Co-Chair: Haohuan Fu, Tsinghua University
Tuesday Dec. 11
8:30		Registration	Lobby
9:00
9:00		Session 2.1 Keynote II	Mugunghwa Hall
		Chair: Kiyoung Choi, Seoul National University
		Future Trends and Next Steps for Reconfigurable Computing
10:00		Dr. Jay (Jeongwook) Kim, Vice President of Samsung Electronics
10:00		Coffee Break	Lobby
10:20
10:20		Session 2.2 Efficient Implementation of Applications on FPGAs	Mugunghwa Hall
		Chair: Ray C.C. Cheung, City University of Hong Kong
	2.2.1	A Fully-Pipelined Expectation-Maximization Engine for Gaussian Mixture Models
		Ce Guo1,2,  Haohuan Fu1,  Wayne Luk2
		1Tsinghua University, 2Imperial College London
	2.2.2	Software/Hardware Framework for Generating Parallel Gaussian Random Numbers Based on the Monty Python Method
		Yuan Li1,  Paul Chow2,  Jiang Jiang3,  Minxuan Zhang1,  Shaojun Wei4
		1National University of Defense Technology, 2University of Toronto, 3Shanghai Jiao Tong University, 4Tsinghua University
	2.2.3	Design Considerations of Real-time Adaptive Beamformer for Medical Ultrasound Research using FPGA and GPU
		Junying Chen,  Alfred C.H. Yu,  Hayden K.-H. So
		University of Hong Kong
	2.2.4	Designing a Hardware in the Loop Wireless Digital Channel Emulator for Software Defined Radio
		Janarbek Matai1,  Pingfan Meng1,  Lingjuan Wu1,  Brad Weals2,  Ryan Kastner1
11:40		1University of California, San Diego, 2Toyon Research Corporation
11:40		Poster Paper Presentations	Mugunghwa Hall
12:00
Tuesday Dec. 11
12:00		Session 2.3 Posters & Coffee Break	Lobby
		Chair: Jongeun Lee, UNIST
	2.3.1	Investigation of Aging Effects in Different Implementations and Structures of Programmable Routing Resources of FPGAs
		Abdulazim Amouri,  Saman Kiamehr,  Mehdi Tahoori
		Karlsruhe Institute of Technology
	2.3.2	Accelerated Evaluation of SEU Failure-in-Time Using Frame-based Partial Reconfiguration
		Yoshihiro Ichinomiya,  Kohei Takano,  Motoki Amagasaki,  Morihiro Kuga,  Masahiro Iida,  Toshinori Sueyoshi
		Kumamoto University
	2.3.3	Introducing Irregularity to Routing Architecture of Structured ASIC for Better Routability
		Insup Shin,  Donkyu Baek,  Youngsoo Shin
		KAIST
	2.3.4	VersaPower: Power Estimation for Diverse FPGA Architectures
		Jeffrey Goeders and Steve Wilton
		University of British Columbia
	2.3.5	Pipeline Frequency Boosting: Hiding Dual-Ported Block RAM Latency using Intentional Clock Skew
		Alexander Brant,  Ameer Abdelhadi, Aaron Severance, Guy G.F. Lemieux
		University of British Columbia
	2.3.6	Acceleration of Fault Attack Emulation by Consideration of Fault Propagation
		Armin Krieg1,  Johannes Grinschgl1,  Christian Steger1,  Reinhold Weiss1,  Holger Bock2,  Josef Haid2
		1Graz University of Technology, 2Infineon Austria AG
	2.3.7	Implementation of a Volume Rendering on Coarse-grained Reconfigurable Multiprocessor
		Seunghun Jin,  Sangheon Lee,  Moo-Kyoung Chung,  Yeongon Cho,  Soojung Ryu
		Samsung Advanced Institute of Technology
	2.3.8	Area Constraint Propagation in High Level Synthesis
		Razvan Nane,  Vlad-Mihai Sima,  Koen Bertels
		Delft University of Technology
	2.3.9	A Hardware Security Module for Quadrotor Communication
		Abdulhadi Shoufan
		Khalifa University of Science, Technology and Research
	2.3.10	A New Hardware Coprocessor for Accelerating Notification-Oriented Applications
		Eduardo Peters,  Ricardo Jasinski,  Volnei Pedroni,  Jean Simão
12:40		Federal University of Technology - Paraná (UTFPR)
12:40		Lunch	Hoam Faculty House
14:00
Tuesday Dec. 11
14:00		Session 2.4 Reconfigurable Architectures for Parallel Computing	Mugunghwa Hall
		Chair: Lesley Shannon, Simon Fraser University
	2.4.1	VENICE: A Compact Vector Processor for FPGA Applications
		Aaron Severance and Guy Lemieux
		University of British Columbia
	2.4.2	A Partially Reconfigurable Architecture Supporting Hardware Threads
		Ying Wang1,  Jian Yan1,  Xuegong Zhou1,  Lingli Wang1,  Wayne Luk2,  Chenglian Peng1,  Jiarong Tong1
		1Fudan University, 2Imperial College London
	2.4.3	Software-Managed Automatic Data Sharing for Coarse-Grained Reconfigurable Coprocessors
		Toan X. Mai and Jongeun Lee
		Ulsan National Institute of Science and Technology
	2.4.4	Graph Minor Approach for Application Mapping on CGRAs
		Liang Chen and Tulika Mitra
15:20		National University of Singapore
15:20		Demo Paper Presentations	Mugunghwa Hall
15:30
Tuesday Dec. 11
15:30		Session 2.5 Demo & Coffee Break	Lobby
		Chair: Jeong-A Lee, Chosun University
		Co-Chair: Suhaib A. Fahmy, Nanyang Technological University
	2.5.1	Dynamic Power Control with a Heterogeneous Multi-Core System Using a 3-D Wireless Inductive Coupling Interconnect
		Yusuke Koizumi1,  Hideharu Amano1,  Hiroki Matsutani1,  Noriyuki Miura1,  Tadahiro Kuroda1,  Ryuichi Sakamoto2,  Mitaro Namiki2,  Kimiyoshi Usami3,  Masaaki Kondo4,  Hiroshi Nakamura5
		1Keio University, 2Tokyo University of Agriculture and Technology, 3Shibaura Institute of Technology, 4University of Electro-Cmmunications, 5University of Tokyo
	2.5.2	Area-Time Estimation of C-based Functions for Design Space Exploration
		Yan Lin Aung,  Siew Kei Lam,  Thambipillai Srikanthan
		Nanyang Technological University
	2.5.3	An Island-Style-Routing Compatible Fault-Tolerant FPGA Architecture with Self-Repairing Capabilities
		Hasan Baig and Jeong-A Lee
		Chosun University
	2.5.4	Streamed High Dynamic Range Imaging
		Donald Bailey
		Massey University
	2.5.5	SimXMD: Integrated Debugging of C Code and Hardware Components
		Ruediger Willenberg and Paul Chow
16:20		University of Toronto
Tuesday Dec. 11
15:30		Session 2.5 PhD Forum & Coffee Break	Lobby
		Chair: Kiyoung Choi, Seoul National University
		Co-Chair: Jason Anderson, University of Toronto
	2.5.6	Constraint-Aware Synthesis of Embedded Applications on Reconfigurable Platforms
		Sharad Sinha (Advisor: Thambipillai Srikanthan)
		Nanyang Technological University
	2.5.7	Reconfigurable Computing with the Partitioned Global Address Space Model
		Ruediger Willenberg (Advisor: Paul Chow)
		University of Toronto
	2.5.8	Low Complexity Spectral Montgomery Modular Multiplication
		Donald Donglong Chen (Advisor: Ray C.C. Cheung)
		City University of Hong Kong
	2.5.9	Shang: A High-level Synthesis Framework with Cross-Level Optimizations
		Hongbin Zheng (Advisor: Dihu Chen)
		Sun Yat-sen University, China
	2.5.10	Scalable Reconfigurable Computation
		Kermin Elliott Fleming (Advisor: Arvind)
		Massachusetts Institute of Technology
	2.5.11	FPGA Architectures and CAD Algorithms for Low Energy Applications
		Assem A. M. Bsoul (Advisor: Steven J.E. Wilton)
		University of British Columbia
	2.5.12	Embedded DSP Block as General Purpose Execution Unit
		Hui Yan Cheah (Advisor: Suhaib A. Fahmy)
		Nanyang Technological University
	2.5.13	Multi-layer Floorplanning for Task Scheduled Reconfigurable FPGAs
		Nan Liu (Advisor: Takeshi Yoshimura)
		Waseda University
	2.5.14	FThreads: Bringing Field Programmable Gate Arrays into the World of Computing Through a Threaded Programming Model
		Vincent Mirian (Advisor: Paul Chow)
		University of Toronto
	2.5.15	Customizing Heterogeneous Multi-core Architecture to Application-Specific Processors
		Janarbek Matai (Advisor: Ryan Kastner)
16:20		University of California, San Diego
Tuesday Dec. 11
16:20		Session 2.6 (Special Session) Architectures and Compilers for Future Coarse-Grained Reconfigurable Processors	Mugunghwa Hall
		Chair: Soojung Ryu, Samsung Advanced Institute of Technology
	2.6.1	Design Evaluation of OpenCL Compiler Framework for Coarse-Grained Reconfigurable Arrays
		Hee-Seok Kim1,  Minwook Ahn2,  John Stratton1,  Wen-mei Hwu1
		1University of Illinois at Urbana-Champaign, 2Samsung Advanced Institute of Technology
	2.6.2	SCC based Modulo Scheduling for Coarse-Grained Reconfigurable Processors
		Wonsub Kim,  Donghoon Yoo,  Haewoo Park,  Minwook Ahn
		Samsung Advanced Institute of Technology
	2.6.3	ULP-SRP: Ultra Low Power Samsung Reconfigurable Processor for Biomedical Applications
		Changmoo Kim1,  Mookyoung Chung1,  Yeongon Cho1,  Mario Konijnenburg2,  Soojung Ryu1,  Jeongwook Kim1
		1Samsung Advanced Institute of Technology, 2Holst Centre / imec
	2.6.4	Efficient Performance Scaling of Future CGRAs for Mobile Applications
		Yongjun Park,  Jason Jong Kyu Park,  Scott Mahlke
17:40		University of Michigan
17:40		Announcement of FPT 2013	Mugunghwa Hall
17:50
17:50		Bus to Banquet Place
18:50
18:50		Banquet	Suraon
21:00
Wednesday Dec. 12
8:30		Registration	Lobby
9:00
9:00		Session 3.1 Keynote III	Mugunghwa Hall
		Chair: Jason Anderson, University of Toronto
		What Security and Processor Designers Would Like in FPGAs
10:00		Prof. Ruby B. Lee, Princeton University
10:00		Coffee Break	Lobby
10:20
10:20		Session 3.2 Acceleration of Specific Functions Using FPGAs	Mugunghwa Hall
		Chair: Hayden K.H. So, University of Hong Kong
	3.2.1	ZIP-IO: Architecture for Application-Specific Compression of Big Data
		Sang Woo Jun1,  Kermin E. Fleming1,  Michael Adler2,  Joel Emer1,2
		1MIT, 2Intel Corporation
	3.2.2	Parallelizing Sparse LU Decomposition on FPGAs
		Guiming Wu1,  Xianghui Xie1,  Yong Dou2,  Junqing Sun3,  Dong Wu1,  Yuan Li2
		1State Key Laboratory of Mathematical Engineering and Advanced Computing, 2National University of Defense Technology, 3Marvell Semiconductor
	3.2.3	Minimizing the Error: A Study of the Implementation of an Integer Split-Radix FFT on an FPGA for Medical Imaging
		Mohammad Reza Mohammadnia and Lesley Shannon
		Simon Fraser University
	3.2.4	Low Complexity and Hardware-friendly Spectral Modular Multiplication
		Donald Donglong Chen1,  Gavin Xiaoxu Yao1,  Cetin Kaya Koc2,  Ray C.C. Cheung1
11:40		1City University of Hong Kong, 2University of California, Santa Barbara
11:40		Session 3.3 Design Competition	Mugunghwa Hall
		Chair: Chanho Lee, Soongsil University
12:40		Co-Chair: Haohuan Fu, Tsinghua University
12:40		Closing	Mugunghwa Hall
12:50
14:00		Cypress PSoC Workshop
17:30		Room 207, Engineering Building 301, Seoul National University
14:00		Career Development and Global Research Network Workshop
16:30		Camellia Hall, Hoam Convention Center
Thursday Dec. 13 - Friday Dec. 14
9:00		Xilinx Workshop - Embedded System Design Flow using Zynq
17:00		Room 207, Engineering Building 301, Seoul National University